Electronic design automation (EDA) tools, a category of computer aided design (CAD) tools, are used by electronic circuit designers to create representations of circuit configurations, including representations of cells (e.g., transistors) and the interconnects they drive. EDA tools allow designers to construct a circuit and simulate its performance using a computer and without requiring the costly and lengthy process of fabrication. EDA tools are indispensable for designing modern, very-large-scale integrated circuits (VSLICs). For this reason, EDA tools are in wide use.
During an initial, “design,” stage, circuit designers employ one or more EDA tools to create a logical representation of a desired electronic circuit. After becoming satisfied (typically through simulation) that the logical representation of the circuit operates as intended, the circuit designers then employ EDA tools called “IC compilers” (ICCs) to transform the logical representation (typically embodied in a “netlist”) automatically into a corresponding physical representation of each cell (sometimes called a “macro”) in the circuit on one or more photolithography masks in an “implementation” stage. The implementation stage typically includes two substages: a “placement” substage in which cells are placed relative to one another in circuit layers of an area representing a substrate which will support the cell, and a “routing” substage in which interconnects are routed in interconnect layers among the cells to yield a cohesive IC. Photolithography masks may then be made and used to fabricate layers of IC features on substrates and thereby form the ICs themselves.
Clock planning is typically carried out after the logical representation is defined. In clock planning, a clock tree is created to drive clock ports of each partition defined in the IC. Buffers are placed in the clock tree such that paths to the clock ports are minimized.